AI memory and HBM supply-chain claims due diligence

Turns public semiconductor announcements into a verification checklist when vendors claim novel scaling laws, stacked logic architectures, or nanometer-class equivalence without independent benchmarks. Teams separate marketing nomenclature from manufacturing readiness by demanding yield, thermal, packaging, and third-party validation evidence—patterns highlighted when CNBC reported Huawei's LogicFolding and τ Scaling Law claims alongside analyst skepticism about true 1.4nm-class process breakthroughs without EUV access. The skill also maps export-control context (ASML EUV restrictions) and competitive implications for GPU vendors operating in constrained geographies.

Explores goals, constraints, risks, and design options before committing to a specific implementation path. This technique is most valuable when facing product or UX decisions where the wrong choice is expensive to reverse—new features with uncertain user value, architectural pivots, or cross-functional dependencies where each team has a different mental model of the problem.

Crafts prompts with explicit task framing, role definition, output constraints, citation requirements, and few-shot examples so model responses are consistent, grounded in evidence, and actionable for downstream tasks. Prompt engineering reduces the variability and hallucination risk that comes from under-specified prompts.